In recent years, in the field of display units, displays using various display devices, such as liquid crystal display devices and displays using organic EL (Electroluminescence) elements have been developed. Image quality improvement (increase in the number of gray scales) are demanded for these display devices, and voltage amplitudes of a scanning signal and a gray scale signal tend to be increased. For this reason, each output section of a row driver that drives a scanning line of a display panel and a column driver that drives a data line of the display panel by a gray scale signal has been demanded to be adapted to high voltage.
On the other hand, high-speed transfer, low EMI (Electromagnetic Interference), and the like using a small number of interconnects are demanded for various control signals and a video data signal that are supplied to the row driver (scan driver) and the column driver (data driver) from a display controller. Thus, amplitudes of those signals are being reduced. Inside the row driver and the column driver as well, a fine process is adopted in order to reduce an increase in the area (increase in the cost) of a logic circuit that processes a data amount that will increase due to high definition and an increase in the number of gray scales, and a power supply voltage of the logic circuit tends to be reduced due to the fine process. That is, lowering of voltages of input sections of the row driver and the column driver and a high voltage of output sections of the row driver and the column driver are demanded.
For this reason, in a level shift circuit that converts a low voltage signal of its input unit to a high-voltage signal of its output unit, the low-amplitude signal must be converted to the high-amplitude signal at high speed.
As a configuration that performs level conversion of a low-amplitude signal to a high-amplitude signal at high speed, Patent Document 1, for example, discloses a configuration including a first converter 100, a second converter 200, and a latch unit 300, as shown in FIG. 11 (which is cited from FIG. 6 of Patent Document 1). The first converter includes a level converting unit 110, a delay unit 120, a self reset unit 130. The level converting unit 110 outputs a level converted signal having a level different from a level of an input signal according to the input signal. The delay unit 120 delays the level converted signal from the level converting unit 110 by a preset delay. The self reset unit 130 generates a reset signal responsive to the level-shifted signal delayed by the delay unit 120, and provides the reset signal to the level conversion unit 110, thereby setting a pulse width of the level-shifted output signal to the sum of the set delay and an internal operation delay. The second converter 200 includes a level converting unit 210, a delay unit 220, and a self reset unit 230.
Referring to FIG. 11, when an input signal DOU is applied like a waveform Apos in FIG. 12 (cited from FIG. 9 of Patent Document 1), the first converter 100 outputs a first converted signal B named as DOUO like a waveform B in FIG. 12 in response to a rising edge of the waveform Apos as indicated by reference symbol A1. Extension or reduction of a pulse width D1 of the first converted signal B is achieved by adjusting the number of inverters that constitute the delay unit 120. A pMOS transistor 331 in the latch unit 300 is made conductive when the waveform B is transitioned to a Low level. A High level of a second supply voltage VDDQ is applied to an input end of an inverter 333 that constitutes a latch L2. The inverter 333 performs an inverting operation to output a Low-level signal as shown in a waveform D in FIG. 12 through an output end named as DOUT. The Low-level signal is continuously maintained by a latch operation of the latch L2 even if the pMOS transistor 331 is made nonconductive by the waveform B that is returned to a High level. When the latch L2 is set to output the Low-level signal, the set operation is maintained until the operation is reset by a turning on operation of the nMOS transistor 332. Referring to the waveform D in FIG. 12, when the waveform Apos reaches a High level, the waveform D is immediately transitioned to a Low level. The output signal thus responses at the rising edge of the input signal at high speed. When an input signal DOD is applied like a waveform Aneg in FIG. 12, the second converter 200 outputs a second converted signal C like a waveform C in FIG. 12 in response to a rising edge of the waveform Aneg as indicated by reference symbol A2. When the waveform C is transitioned to a High level, an nMOS transistor 332 in the latch unit 300 is made conductive. Thus, the input end of the inverter 333 that constitutes the latch L2 goes Low, so that the latch L2 is reset. A High-level signal is output to the output end named as DOUT due to the operation of the inverter 333, as shown in the waveform D in FIG. 12. Even if the nMOS transistor 332 is made nonconductive, the High-level signal is continuously maintained due to the latch operation of the latch L2. When the latch L2 is reset so that the High-level signal is output, the reset operation is maintained until the pMOS transistor 331 is made conductive. Referring to the waveform D in FIG. 12, an output signal DOUT output as a single-ended signal has a pulse width matching the pulse width of each of the differential input signals DOU and DOD. An overall delay time of T1+T2 needed for level conversion is minimized, so that the output signal DOUT has a high-speed response characteristic.    [Patent Document 1] JP Patent Kokai Publication No. JP-P2003-152526A (FIGS. 6 and 9)